The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of a gate electrode over a gate dielectric layer in semiconductor devices.
Fabrication of a semiconductor device and an integrated circuit thereof begins with a semiconductor substrate and employs film formation, ion implantation, photolithographic, etching and deposition techniques to form various structural features in or on a semiconductor substrate to attain individual circuit components which are then interconnected to ultimately form an integrated semiconductor device. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for large-scale and ultra large-scale integration devices employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is typically a thin gate dielectric material, usually referred to as a gate oxide, and a conductive gate comprising conductive polysilicon or another conductive material. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices employing both p-channel and n-channel devices are formed on a common substrate. MOS technology offers advantages of significantly reduced power density and dissipation as well as reliability, circuit performance and cost advantages.
The drive towards increased miniaturization and the resultant limits of conventional gate oxide layers have served as an impetus for the development of newer, high dielectric constant (xe2x80x9chigh-Kxe2x80x9d) materials as substitutes for conventional silicon dioxide-based gate oxide layers. Since the drain current in a MOS device is inversely proportional to the gate oxide thickness, the gate oxide is typically made as thin as possible commensurate with the material""s breakdown field and reliability.
Decreasing the thickness of the gate oxide layer between the gate electrode and the source/drain extension regions together with the relatively high electric field across the gate oxide layer, can undesirably cause charge carriers to tunnel across the gate oxide layer. This renders the transistor xe2x80x9cleakyxe2x80x9d, degrading its performance. To alleviate this problem, high-K dielectric materials are used as the gate insulator. Herein, a high-K gate oxide may be referred to as a high-K gate dielectric material layer, in order to emphasize that the gate dielectric comprises a high-K dielectric material rather than silicon dioxide.
One problem which has been encountered in integrating high-K dielectric materials into CMOS devices, and other semiconductor devices such as EEPROMs and other flash memory devices, is the undesirable interaction between many high-K dielectric materials and the silicon used in other semiconductor device structures. Of particular concern is the interaction between the polysilicon typically used for the gate electrode and the high-K material used for the high-K gate dielectric material. Such undesirable interactions are not confined to CMOS devices, but may also occur between polysilicon gate structures and high-K dielectric insulation layers in SONOS-type devices such as the MIRRORBIT(trademark) flash memory cell available from Advanced Micro Devices, Inc., Sunnyvale, California, and in floating gate flash memory cells.
One of the undesirable interactions which may occur is the reduction of the metal oxide of a high-K gate dielectric material by hydrogen used in forming a polysilicon gate electrode on a high-K gate dielectric material layer.
Hence, it would be highly advantageous to develop a process that would permit the use of optimum materials in the formation of the gate electrode structure. It would also be highly advantageous to develop methodologies capable of optimum MOS transistor formation. Accordingly, there exists a need for a process of manufacturing MOS semiconductor devices with a high-K dielectric material layer that improves device performance, while avoiding undesirable interactions between elements such as polysilicon in gate electrodes and the high-K gate dielectric materials. In particular, a need remains for a process of forming a polysilicon gate electrode over a high-K gate dielectric material while avoiding reduction of the metal oxide at the interface between the polysilicon gate electrode and the high-K dielectric layer.
The present invention relates to a process of fabricating a semiconductor device including a high-K dielectric material for a gate dielectric, including steps of providing a semiconductor substrate; depositing on the semiconductor substrate a layer comprising a high-K gate dielectric material; depositing on the layer comprising a high-K gate dielectric material a polysilicon gate electrode layer, wherein the step of depositing the polysilicon gate electrode layer includes providing non-reducing conditions in a CVD apparatus. In one embodiment, the non-reducing conditions include providing a source of silicon which is free of hydrogen. In another embodiment, the non-reducing conditions include providing controlled oxidizing conditions in the CVD apparatus. In another embodiment, the non-reducing conditions include providing a source of silicon which contains a relatively reduced amount of hydrogen and providing oxidizing conditions in the CVD apparatus.
Thus, the present invention overcomes the problem of forming a polysilicon gate electrode over a high-K gate dielectric material while avoiding reduction of the metal oxide at the interface between the polysilicon gate electrode and the high-K dielectric layer.